In the picture above, you can see the rows of the memory array. Each of it has 1 byte.
A noteworthy thing is that this ram-design uses the fewest amount of npn transistors (BC847). Every cell has a word line, two write lines, one read line and the two power pins.
The big board on the bottom, connects all write and read pins. The 3 Pins on the right side, are the word line and the power.
A schematic illustration of this circuit:
In my case, I used some BC847 with these resistors. (The Input resistors are placed on the sensor module, which drives the columns) And you need a second module to drive the rows (WL). For this reason, I made a 4 bit decoder.
However, the real circuit is as easy as possible:
This design is stackable. In other words, 8 of these small pieces create “1 byte of memory” with a common WL.